Design Implementation of 32-bit Twin Precision Low Power Re- Configurable Multiplier

In a signal processing like application, the performance of the whole processing is a function of how fast the FFT operation is done .The speed of the operation is directly dependent on efficiency of the multiplier in the design. The paper discusses about a multiplier implementation where the speed of computation is improved by using twin-precision scheme and row decomposition schemes. To lower the dynamic power consumption we have involved the concept of clock gating .The proposed architecture permits the optimization of the speed and power. The design is a purely combinational logic based circuitry internally, involving a clock for data reliability. A comparison between 32 bit and 16-bit multipliers, one working on twin precision scheme compared to regular HPM, shows that the twin-precision multiplier has significant lower power dissipation and 35% higher speed with a trade off in more transistors. The implementation of the design is carried at 32nm and 90nm using Synopsys VCS, DC and ICC.